Shuhang Lyu
Engineering · Purdue University West Lafayette
Publications
21
Citations
85
Est. group size
~2
Recurring co-author estimate
Active years
6
Publishing since 2021
Shuhang Lyu's work focuses on advanced semiconductor packaging, particularly the design, fabrication, and reliability of tiny vertical electrical connections (through-silicon vias and through-glass vias) used to stack computer chips into compact 3D structures. The research also covers related thermal management challenges, such as cooling densely packed chips and predicting mechanical stress in these microscopic structures using experimental characterization and machine learning. This work is relevant to students interested in the physical engineering behind next-generation, high-density computer chip packaging.
Publication output was minimal or absent before 2021 but has grown substantially since 2022, with a notable increase in output from 2024 through 2026.
Generated by claude-sonnet-5 from public bibliographic data · Jul 20, 2026
- Reliability Investigation for Scaling 3D Interconnects in Advanced Semiconductor Packaging
IEEE RESOURCE CENTERS · 2026
- Understanding Thermomechanical Response of Scaled Through Silicon Vias for High-density 3D Packaging
Purdue · 2026
- Understanding Thermomechanical Response of Scaled Through Silicon Vias for High-density 3D Packaging
Purdue · 2026
- Novel Metrology For Experimentally Visualizing Cu-Cu Bonding Induced Thermal Stress
2026
- TSV Stress Prediction via Machine Learning Based on EBSD Grain Microstructure
2026
- Scaling effects on the microstructure and thermomechanical response of through silicon vias (TSVs)
Journal of Applied Physics · 2025
- Development of Straight, Small-Diameter, High-Aspect Ratio Copper-Filled Through-Glass Vias (TGV) for High-Density 3D Interconnections
2025
- Reliability and Microstructure Characterization of Through-Silicon Vias (TSV) at Different Aspect Ratios Using EBSD-Raman Spectroscopy
2025
- Bottom-Up Electrodeposition of Small Diameter, High Aspect Ratio Nanotwinned-Copper-Filled Through-Silicon Vias for Ultra High-Density 3D Integration
2025
- Process Development and Characteristics of Small-Diameter (<3 μm), Cobalt-Filled Through Silicon Vias (TSVs) for High-Density 3D Chip Stacking
2025
- Numerical modelling and analysis of porous surface-enhanced jet cooling using copper inverse opals in single-phase flow
Flow · 2024
- Thermomechanical Modeling and Stress Analysis of Copper Inverse Opal (CIO) Structure for Capillary-Fed Boiling
IEEE Transactions on Components Packaging and Manufacturing Technology · 2024
- Thermo-Mechanical Reliability Analysis and Raman Spectroscopy Characterization of Sub-micron Through Silicon Vias (TSVs) for Backside Power Delivery in 3D Interconnects
2024
- Thermal Analysis of Dual-sided Cooling for Backside Power Delivery Networks (BSPDN) on 2.5D Glass/Silicon Interposer Package
2024
- A Novel Copper Microporous-Assisted Bonding Method for Fine-Pitch Cu/Sn Microbump 3D Interconnects
2024
- Purdue×2
- Journal of Applied Physics×1
- Chemical Physics Letters×1
- Langmuir×1
- Flow×1
- Gerald Beyer
Engineering · The Ohio State University
- Shuwei He
Engineering · The Ohio State University
- Arvind Sundaram
Engineering · Purdue University West Lafayette
- John A. Wu
Engineering · Purdue University West Lafayette
- Chetan Jois
Engineering · Purdue University West Lafayette
This profile was generated automatically from public scholarly data (OpenAlex). Group size and activity levels are estimates derived from co-authorship patterns.
Last updated Jul 20, 2026.
Claim or correct this profile