Gerald Beyer
Engineering · The Ohio State University
Publications
365
Citations
4,233
Est. group size
~3
Recurring co-author estimate
Active years
51
Publishing since 1976
Gerald Beyer works on advanced chip packaging and interconnect technologies, focusing on how to physically connect and stack computer chips at extremely small scales. His recent work centers on wafer-to-wafer and die-to-wafer 'hybrid bonding' techniques that let chips be stacked and connected with metal interconnects spaced as little as a few hundred nanometers apart, which is relevant to building faster and more compact 3D chip stacks used in computing hardware, including emerging applications like quantum computing.
Publication output has fluctuated over the past decade but shows a recent upward trend, rising from around 9 papers per year in 2022-2023 to 16-17 in 2024-2025.
Generated by claude-sonnet-5 from public bibliographic data · Jul 20, 2026
- Accuracy in Infrared Overlay Metrology
2026
- Characterization of FOWLP Process Using Temporary Bonding Materials on Carrier with Very Low Die Shift
Zenodo (CERN European Organization for Nuclear Research) · 2025
- Characterization of FOWLP Process Using Temporary Bonding Materials on Carrier with Very Low Die Shift
Zenodo (CERN European Organization for Nuclear Research) · 2025
- 2 μm Pitch Direct Die-to-Wafer Hybrid Bonding Using Surface Protection During Wafer Thinning and Die Singulation
Zenodo (CERN European Organization for Nuclear Research) · 2025
- 2 μm Pitch Direct Die-to-Wafer Hybrid Bonding Using Surface Protection During Wafer Thinning and Die Singulation
Zenodo (CERN European Organization for Nuclear Research) · 2025
- Challenges and Mitigations of Microbumps Pitch Scaling for Chiplet Applications
IEEE Transactions on Components Packaging and Manufacturing Technology · 2025
- Etch development of Through-Dielectric-Via for Wafer Reconstruction with Gap-Fill Oxide
2025
- Integration of Through-Dielectric-Via on Buried Power Rail and Slit Nano Through-Silicon-Via for Enhanced Backside Connectivity
2025
- Characterization of FOWLP Process Using Temporary Bonding Materials on Carrier with Very Low Die Shift
2025
- Wafer-to-Wafer Hybrid Bonding Technology with 200nm Interconnect Pitch
2025
- 2 μm Pitch Direct Die-to-Wafer Hybrid Bonding Using Surface Protection During Wafer Thinning and Die Singulation
2025
- High-Density Wafer Level Connectivity Using Frontside Hybrid Bonding at 250nm Pitch and Backside Through-Dielectric Vias at 120nm Pitch After Extreme Wafer Thinning
2025
- Wafer-to-Wafer Bonding with Saddle-Shaped Wafers
2025
- Impact of Temporary Substrates & Adhesives on Die-to-Wafer Overlay
2025
- Self-formed Barrier using Cu-Mn Alloy Seed applied to a 400nm Pitch Wafer-to-Wafer Hybrid Bonding Technology
2025
- ECS Journal of Solid State Science and Technology×5
- Zenodo (CERN European Organization for Nuclear Research)×4
- Microelectronic Engineering×3
- 2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)×3
- 2016 6th Electronic System-Integration Technology Conference (ESTC)×3
- Shuhang Lyu
Engineering · Purdue University West Lafayette
- Shuwei He
Engineering · The Ohio State University
- Arvind Sundaram
Engineering · Purdue University West Lafayette
- John A. Wu
Engineering · Purdue University West Lafayette
- Ganesh Subbarayan
Engineering · Purdue University West Lafayette
This profile was generated automatically from public scholarly data (OpenAlex). Group size and activity levels are estimates derived from co-authorship patterns.
Last updated Jul 19, 2026.
Claim or correct this profile