Irith Pomeranz
Computer Science · Purdue University West Lafayette
Publications
815
Citations
11,142
Est. group size
~2
Recurring co-author estimate
Active years
38
Publishing since 1989
Irith Pomeranz works on testing digital hardware circuits (chips) to make sure they function correctly and to detect manufacturing defects or aging-related faults over time. Her research develops methods for generating test sequences, compacting tests to reduce their number while keeping fault coverage high, and diagnosing the location of faults in a circuit, including effects related to chip aging and switching activity. This work is relevant to students interested in hardware reliability, VLSI design-for-testability, and computer-aided design tools for integrated circuits.
Publication output has remained fairly steady over the last decade, fluctuating between about 12 and 23 papers per year without a clear long-term increase or decrease.
Generated by claude-sonnet-5 from public bibliographic data · Jul 20, 2026
- Aging Aware Steepening of the Fault Coverage Curve of a Single Functional Test Sequence
IEEE Access · 2026
- Buffered Bounded Transparent Scan for Test Generation
IEEE Access · 2026
- Varying Periods of In-Field Testing With Storage- and Counter-Based Logic Built-In Self-Test
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2025
- Test Templates to Guide Test Generation for Single-Cycle Gate-Exhaustive Faults
ACM Transactions on Design Automation of Electronic Systems · 2025
- Functionally-Possible Subcircuit-Based Tests for Path Delay Faults
IEEE Access · 2025
- Arranging a Pool of Functional Test Sequences for Variable In-Field Test Periods
IEEE Access · 2025
- Chip Aging and Transition Faults With High Switching Activities Under Scan-Based Tests
IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2025
- Hazard-Based Functionally Possible Transition Faults With High Functional Switching Activities
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2025
- DTGx2: Dual Target Diagnostic Test Generation
ACM Transactions on Design Automation of Electronic Systems · 2025
- DYCOCO: Dynamic Configuration-Based Test Compaction
IEEE Access · 2025
- Modular Functional Test Sequences for Test Compaction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2025
- Reverse Steepening of a Fault Coverage Curve
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2025
- Multicycle Tests for Functionally Possible Two-Cycle Gate-Exhaustive Faults
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2025
- Diagnostic Test Compaction of Functional Test Sequences
IEEE Access · 2025
- Functional Logic Diagnosis with Observation Points on Next-State Variables
2025
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems×54
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems×32
- ACM Transactions on Design Automation of Electronic Systems×22
- IEEE Access×12
- IET Computers & Digital Techniques×7
- Qiang Xu
Computer Science · Purdue University West Lafayette
- Irith Pomeranz
Engineering · Purdue University West Lafayette
- T. D. Loveless
Engineering · Indiana University
- C. Chiang
Computer Science · Purdue University West Lafayette
- Chi-Yuan Lo
Engineering · Indiana University
This profile was generated automatically from public scholarly data (OpenAlex). Group size and activity levels are estimates derived from co-authorship patterns.
Last updated Jul 20, 2026.
Claim or correct this profile