Akul Malhotra
Engineering · Purdue University West Lafayette
Publications
24
Citations
75
Est. group size
~2
Recurring co-author estimate
Active years
8
Publishing since 2019
Akul Malhotra works on hardware for running artificial intelligence (AI) more efficiently, focusing on 'in-memory computing' — a design approach where data storage and computation happen in the same physical location to speed up AI calculations and reduce energy use. Much of the work addresses making these memory-based AI chips more reliable and fault-tolerant, especially for low-precision neural networks (binary and ternary, meaning they use very simplified numerical representations) and emerging memory technologies like resistive RAM, STT-MRAM, and ferroelectric transistors.
Publication output has grown notably over the last decade, rising from sporadic activity before 2022 to a peak of 7 publications in 2025.
Generated by claude-sonnet-5 from public bibliographic data · Jul 20, 2026
- SCION: A Comprehensive Simulation Framework for Charge-based In-Memory Computing for Rapid Evaluation of Hardware Non-Idealities and DNN Accuracy
2026
- TWINN: Training-Free Weight-Input Flipping for Mitigating Crossbar Non-Idealities in Binary Neural Network Accelerators
IEEE Transactions on Circuits and Systems I Regular Papers · 2025
- ReTern: Exploiting Natural Redundancy and Sign Transformations for Enhanced Fault Tolerance in Compute-in-Memory-Based Ternary LLMs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2025
- CREST-CiM: Cross-Coupling-Enhanced Differential STT-MRAM for Robust Computing-in-Memory in Binary Neural Networks
2025
- ReTern: Exploiting Natural Redundancy and Sign Transformations for Enhanced Fault Tolerance in Compute-in-Memory based Ternary LLMs
arXiv (Cornell University) · 2025
- 1.58-b FeFET-Based Ternary Neural Networks: Achieving Robust Compute-In-Memory With Weight-Input Transformations
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits · 2025
- Weight Transformations in Bit-Sliced Crossbar Arrays for Fault Tolerant Computing-in-Memory: Design Techniques and Evaluation Framework
arXiv (Cornell University) · 2025
- Weight Transformations in Bit-Sliced Crossbar Arrays for Fault Tolerant Computing-in-Memory: Design Techniques and Evaluation Framework
arXiv (Cornell University) · 2025
- BNN-Flip: Enhancing the Fault Tolerance and Security of Compute-in-Memory Enabled Binary Neural Network Accelerators
2024
- Memory Faults in Activation-sparse Quantized Deep Neural Networks: Analysis and Mitigation using Sharpness-aware Training
arXiv (Cornell University) · 2024
- SiTe CiM: Signed Ternary Computing-in-Memory for Ultra-Low Precision Deep Neural Networks
arXiv (Cornell University) · 2024
- BinSparX: Sparsified Binary Neural Networks for Reduced Hardware Non-Idealities in Xbar Arrays
arXiv (Cornell University) · 2024
- Fault Tolerant In-Memory Computing based on Emerging Technologies for Ultra-Low Precision Edge AI Accelerators
2024
- TFix: Exploiting the Natural Redundancy of Ternary Neural Networks for Fault Tolerant In-Memory Vector Matrix Multiplication
2023
- RIBoNN: Designing Robust In-Memory Binary Neural Network Accelerators
2022
- arXiv (Cornell University)×10
- IEEE Journal on Exploratory Solid-State Computational Devices and Circuits×2
- IEEE Transactions on Nanotechnology×1
- IEEE Transactions on Circuits and Systems I Regular Papers×1
- IEEE Transactions on Circuits & Systems II Express Briefs×1
- Indranil Chakraborty
Engineering · Purdue University West Lafayette
- Hongyi Dou
Engineering · Purdue University West Lafayette
- Haitong Li
Engineering · Purdue University West Lafayette
- Amogh Agrawal
Engineering · Purdue University West Lafayette
- Karam Cho
Engineering · Purdue University West Lafayette
This profile was generated automatically from public scholarly data (OpenAlex). Group size and activity levels are estimates derived from co-authorship patterns.
Last updated Jul 20, 2026.
Claim or correct this profile