Cheng‐Kok Koh

Engineering · Purdue University West Lafayette

Established · publishing since 1976Rising activity

VLSI and FPGA Design Techniques Low-power high-performance VLSI design VLSI and Analog Circuit Testing Interconnection Networks and Systems 3D IC and TSV technologies

Publications

245

Citations

4,492

Est. group size

Recurring co-author estimate

Active years

Publishing since 1976

Research summary

AI-generated

Cheng-Kok Koh works on computer-aided design (CAD) tools for building computer chips, focusing on VLSI (very-large-scale integration) circuit design. Much of the recent work centers on clock tree synthesis (designing the wiring that distributes timing signals across a chip) and related timing and layout optimization algorithms for large, complex chip designs. This research supports the automated tools chip designers use to make circuits faster, more reliable, and easier to manufacture at advanced technology scales.

VLSI chip design automationClock tree synthesis and timing optimizationAlgorithms for circuit layout and interconnect3D integrated circuits and TSV technologyLow-power and high-performance circuit design

Publication output has been modest but fairly steady over the last decade, with a few gap years and a recent uptick in output.

Generated by claude-sonnet-5 from public bibliographic data · Jul 20, 2026

Publication cadence

Publications per year over the last 10 years — averaging 2.0/year recently

Recent publications

A Scalable, Memory-Efficient Algorithm for Minimum Cycle Mean Calculation in Directed Graphs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2021
A Scalable Buffer Queue Sizing Algorithm for Latency Insensitive Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2020
Clustering of flip-flops for useful-skew clock tree synthesis
2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC) · 2018
Clustering of flip-flops for useful-skew clock tree synthesis
Journal of International Crisis and Risk Communication Research · 2018
Scalable Construction of Clock Trees With Useful Skew and High Timing Quality
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2018
Clock Tree Construction based on Arrival Time Constraints
2017
Delay-driven layer assignment for advanced technology nodes
2017
Construction of Latency-Bounded Clock Trees
2016
MCMM clock tree optimization based on slack redistribution using a reduced slack graph
2016
Construction of Reconfigurable Clock Trees for MCMM Designs Using Mode Separation and Scenario Compression
ACM Transactions on Design Automation of Electronic Systems · 2016
Fast clock scheduling and an application to clock tree synthesis
Integration · 2016

Publishes in

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems×4
arXiv (Cornell University)×2
IEEE Transactions on Systems Man and Cybernetics Systems×1
Integration×1
ACM Transactions on Design Automation of Electronic Systems×1

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This profile was generated automatically from public scholarly data (OpenAlex). Group size and activity levels are estimates derived from co-authorship patterns.

Last updated Jul 20, 2026.

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