Anand Raghunathan
Computer Science · Purdue University West Lafayette
Publications
519
Citations
20,158
Est. group size
~11
Recurring co-author estimate
Active years
32
Publishing since 1995
Anand Raghunathan works on making computer hardware and machine learning systems more efficient, focusing on chip design, low-power circuits, and specialized hardware for running AI models faster and with less energy. Recent work centers on optimizing deep learning inference and training (including quantization, compression, and hardware accelerators) for edge devices and large language models. His research sits at the intersection of computer architecture, VLSI (chip) design, and machine learning systems.
Publication output was higher and fairly steady between 2017 and 2022 (roughly 14-22 papers/year) but has declined to under 10 per year from 2023 onward.
Generated by claude-sonnet-5 from public bibliographic data · Jul 20, 2026
- SPARQLe: Sub-Precision Activation Representation for Quantized LLM Inference
arXiv (Cornell University) · 2026
- SPARQLe: Sub-Precision Activation Representation for Quantized LLM Inference
arXiv (Cornell University) · 2026
- A3D: Agentic AI flow for autonomous Accelerator Design
arXiv (Cornell University) · 2026
- A3D: Agentic AI flow for autonomous Accelerator Design
arXiv (Cornell University) · 2026
- Characterizing VLA Models: Identifying the Action Generation Bottleneck for Edge AI Architectures
arXiv (Cornell University) · 2026
- Characterizing VLA Models: Identifying the Action Generation Bottleneck for Edge AI Architectures
arXiv (Cornell University) · 2026
- Efficient SoC Power Estimation With Machine Learning
IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2026
- ML-Power: Machine Learning based Power Estimation for SoCs
2025
- Softprox: A Post-Finetuning Methodology to Mitigate Softmax Bottlenecks in Transformer Workloads
IEEE transactions on circuits and systems for artificial intelligence. · 2025
- LO-BCQ: Block Clustered Quantization for 4-bit (W4A4) LLM Inference
ArXiv.org · 2025
- Proceedings of the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems
2025
- Analysis of relaxation characteristics of multi-bolted connections under the transverse cyclic load
Scientific insights and discoveries review · 2024
- LRMP: Layer Replication with Mixed Precision for spatial in-memory DNN accelerators
Frontiers in Artificial Intelligence · 2024
- MixTrain: accelerating DNN training via input mixing
Frontiers in Artificial Intelligence · 2024
- Input Compression with Positional Consistency for Efficient Training and Inference of Transformer Neural Networks
Lecture notes in computer science · 2024
- arXiv (Cornell University)×38
- IEEE Transactions on Very Large Scale Integration (VLSI) Systems×12
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems×5
- ACM Transactions on Embedded Computing Systems×4
- IEEE Transactions on Multi-Scale Computing Systems×3
- Akash Kumar
Computer Science · Purdue University West Lafayette
- Geoffrey Brown
Computer Science · Indiana University
- Goutham Kalikrishna Reddy Kuncham
Computer Science · The Ohio State University
- Ryan Newton
Computer Science · Purdue University West Lafayette
- Artem Pelenitsyn
Computer Science · Purdue University West Lafayette
This profile was generated automatically from public scholarly data (OpenAlex). Group size and activity levels are estimates derived from co-authorship patterns.
Last updated Jul 20, 2026.
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